The present invention is directed generally to semiconductor structures and, more particularly, to a metal gate electrode formed in combination with elevated salicided source/drain regions.
Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applicability and numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
A typical MOS semiconductor device generally includes a gate electrode, which acts as a conductor, to which an input signal is typically applied via a gate terminal. Heavily doped source/drain regions are formed in a semiconductor substrate and are respectively connected to source and drain terminals. A channel region is formed in the semiconductor substrate beneath the gate electrode and separates the source/drain regions. The channel is typically lightly doped with a dopant type opposite that of the source/drain regions. The gate electrode is physically separated from the semiconductor substrate by a gate insulating layer, typically an oxide layer such as SiO2. The insulating layer is provided to prevent current from flowing between the gate electrode and the source/drain regions or channel region.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode, a transverse electric field is set up in the channel region. By varying the transverse electric field, it is possible to modulate the conductance of the channel region between the source region/drain regions. In this manner an electric field controls the current flow through the channel region. This type of device is commonly referred to as a MOS field-effect-transistors (MOSFET).
Semiconductor devices, like the one described above, are used in large numbers to construct most modern electronic devices. In order to increase the capability of such electronic devices, it is necessary to integrate ever increasing numbers of such devices into a single silicon wafer. As the semiconductor devices are scaled down (i.e., made smaller) and in order to form a larger number of devices on a given surface area, the structure of the devices and fabrication techniques used to make such devices must be altered.
Several objectives influence MOSFET design and fabrication. First, there is a desire to reduce the dimensions of the MOSFET. Increasing the number of individual MOSFETs that can be placed onto a single silicon chip or die produces increased functionality per chip. Second, there is a continual desire to improve performance, and particularly the speed, of the MOSFET transistors. This pursuit is manifested in shorter conduction channel lengths and in efforts to obtain low contact at the MOSFET junctions. These aspects offer increased MOSFET speed and allow for a greater number of operations to be performed by the MOSFET in less time. MOSFETs are used in great quantity in computers where the push to obtain higher operation cycle speeds demands faster MOSFET performance. Lastly, there exists a constant need to minimize costly MOSFET fabrication steps.
Many prior MOSFETs designs have metal gate electrodes. However, with the challenges that accompany sub-micron gate alignment and modern high-temperature processing, metal gate electrodes have often been replaced with polysilicon gate electrodes. One difficulty faced in making semiconductor structures having metal gates is that the melting point of the metal is below the temperatures applied to the structure during high temperature thermal annealing which is used for various purposes during fabrication. Polysilicon, in contrast, has a much higher melting point. Thus, polysilicon is often used for gate electrodes. However, metal is desirable because of its conductivity and its ability to produce a stronger electric field.
Conventional approaches have encountered difficulty trying to maintain performance in the face of decreasing size and increasing density of devices. In attempting to overcome these hurdles, it is equally desirable to keep costly processing steps to a minimum. Therefore, it is desirable to provide a semiconductor structure and provide a process for its manufacture to address the above identified problems.
Generally, the present invention relates to a semiconductor structure and a process for its manufacture. In one embodiment, a semiconductor structure is provided. The semiconductor structure comprises first and second gate dielectric layers formed on a semiconductor substrate between nitride spacers. A metal gate electrode is formed on the gate dielectric layers, along with lightly-doped drain regions and source/drain regions are disposed in the substrate and aligned with the electrode and spacers. A silicide contact layer is disposed over an epitaxial layer on the substrate over the source/drain regions. The metal gate electrode is aligned using a polysilicon alignment structure, which permits high temperature processing before the metal is deposited.
In another embodiment, a process is provided for manufacturing a semiconductor structure. The process comprises forming a polysilicon alignment structure on a substrate. The polysilicon alignment structure permits high temperature processing before a metal for a gate electrode is deposited. A first concentration of a first dopant species is implanted into the substrate at a first energy level, whereby lightly doped drain regions are formed in the substrate and aligned with the alignment structure. Nitride spacers are formed on sides of the alignment structure, and a second concentration of a second dopant species is implanted into the substrate at a second energy level, whereby source and drain regions are formed in the substrate and aligned with the alignment structure. Adjacent to the spacers, an epitaxial layer is grown on the substrate, and the polysilicon alignment structure is thereafter removed, thereby forming a trench between the spacers. First and second gate dielectric layers are formed in the trench, and a silicide layer is formed on the epitaxial layer. Lastly, a metal gate electrode is formed in the trench.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.